1. Field of the Invention
The present invention relates to a semiconductor device having a transmission control circuit in which a signal transmission circuit for transmitting a predetermined signal through a signal bus is provided, and particularly relates to a semiconductor device having a transmission control circuit which is configured to perform timing control using a replica circuit when transmitting the predetermined signal through the signal bus.
2. Description of Related Art
A semiconductor memory device such as a DRAM (Dynamic Random Access Memory) is generally provided with a transmission control circuit for controlling a transmission timing of a signal. Since an increase in capacity of the semiconductor memory device poses a problem of delay in a signal bus for transmitting signals, it is important to properly adjust delay time of a control signal for defining an operation timing of the transmission control circuit so as to obtain sufficient margin for a signal having large transmission delay. However, when device characteristics and temperature characteristics of the semiconductor device fluctuate for the operation timing based on the adjusted delay time, the margin often becomes improper due to an increase or decrease in the transmission delay. That is, when the transmission delay of the signal bus decreases relative to the above operation timing, the proper transmission characteristics cannot be obtained due to over-margin, while when the transmission delay of the signal bus increases relative to the above operation timing, insufficiency of the margin causes that proper operation is not assured, so that there is an concern of an increase in failures.
In a read operation of the DRAM, for example, when read data of a memory cell array is transmitted through the signal bus and outputted, its output term is controlled by a pulse of a control signal for which a proper delay time is set. At this point, since the operation timing of the transmission control circuit and the transmission timing of the signal bus are not identical to each other due to fluctuations in device characteristics and temperature characteristics, the output of the read data transmitted during the output term set by the control signal is hindered and there is a possibility that failures in the DRAM increase.
Meanwhile, a configuration including a replica circuit having the same characteristics as a certain circuit has been conventionally proposed (see, for example, Laid-open Japanese Patent Publication No. 2006-12229). Thus, the above transmission control circuit can be provided with the replica circuit. However, since the conventional replica circuit operates to replace a function of the certain circuit, it is difficult to improve timing control itself of the transmission control circuit and a technique for solving the above problem has not been proposed.